1. Field of the Invention
The present invention relates generally to data protection schemes, and more specifically to protection of the static random access memories (SRAMs) associated with the ICs.
2. Description of the Related Art
In a multi-processor environment, it is important to maintain the states of the memories. More particularly, with respect to cache coherency, a state array, such as a state SRAM associated with an L2 cache of a core multi-processor (CMP), must be protected against errors. FIG. 1 is a simplified diagram illustrating the topology where multiple cores are in communication with a shared L2 cache. Here, cores C0–C3 100-1 through 100-4 share L2 cache 104.
As is generally known, the cache coherency scheme keeps each processor's view of the memory consistent. A processor's access to a cache block is determined by the state of that block in the processor's cache. Cache coherence protocols for shared memory multi-processors provide an array detailing the actions for each combination of the states of the cache. The states of the cache are generally defined through a protocol, such as the Modified, Own, Exclusive, Shared, Invalid (MOESI) protocol.
The number of the multiple cores sharing the L2 cache in core multiple chips is increasing. Additionally, the size of the shared cache is also increasing. Furthermore, in a multithread environment, it may be necessary to track which thread within a core is modifying the line. Thus, the amount of information maintained further increases for the multi-thread environment. Therefore, it is desirable to maintain the reliability of the data in an array, such as the state array for the L2 cache, against single bit and double bit errors.
One scheme for protecting the reliability of the data in the array is the use of a parity bit. However, the parity bit does not offer any means of correcting a detected error. Another scheme for protecting large arrays is the extended Hamming code, i.e., Hamming code plus parity protection. Here, an (8,4) Hamming code is required, where for the four bits being protected, i.e., the modified, own, exclusive and share bits for the MOESI protocol, require four additional bits. One shortcoming of the Hamming code scheme is that an exclusive or (XOR) operation is required to be performed for all the state and error protection bits. That is, a full XOR of the code word is required in order to create the parity bit. Consequently, an XOR gate having eight inputs is needed. Yet another scheme to protect the reliability of the array is to create two copies of the array, i.e., mirror the array, and protect both copies with parity. Under this scheme, 12 bits would be required.
In light of the foregoing, it is desired to implement a scheme to protect the reliability of an array of data from single bit and double bit errors with a minimal amount of bits required to achieve the protection, as well as minimizing the area required for implementation of the protection scheme.